In the manufacture of semiconductor chips, cost is clearly an important concern. Ways are therefore always being looked for to reduce the size of devices in order to allow more devices to fit onto a semiconductor wafer. Also, speed considerations dictate strongly in favor of reduced size. Furthermore, cost is directly impacted by process considerations: especially the number of process steps involved in producing a particular circuit in semiconductor chip form.
Typically, semiconductor devices are built up in layers involving a series of process steps to produce the desired characteristics. For example, a typical semiconductor device such as the device 100 illustrated in FIG. 1, may include a polysilicon gate 110 insulated from the underlying silicon substrate by an oxide layer 112. Two n+ composite regions 114, 116 are shown and may comprise drain and source regions of a NMOS transistor. The device 100 is separated by shallow trench isolation regions 118, 120 from adjacent devices 130, 140, respectively. As mentioned above, the devices 100. 130, 140 are formed in layers. Typically, a silicon substrate is used in which the composite regions 114, 116 are formed by introducing impurities using one of several possible methods. The shallow trench isolation regions 118, 120 are formed as isolators between the devices. Thereafter a silicide layer 150 may be formed by depositing a layer of metallic material such as cobalt or titanium and annealing it to react with the silicon to form a silicide. Thereafter the excess, unreacted cobalt or titanium is removed using an etch process. This is followed by depositing a thick oxide layer (TEOS) 152. In order to provide electrical contacts to specific regions in the device, holes are etched into the TEOS 152 using masking and etching steps, whereafter the holes are filled with metal such as tungsten to define tungsten contacts or plugs 160, 162. A metal layer (metal 1) 170 is then formed on top of the TEOS 152 to contact the contacts 160, 162. In order, for example, to interconnect the polysilicon gate 110 and the composite material 180 of adjacent device 140, contacts 182, 184 are provided to the polysilicon gate 110 and composite 180, respectively, as shown in the plan view of FIG. 2. The metal 1 layer 170 is formed to provide a metal interconnect between the contact 182 and contact 184.
It will be appreciated that the formation of the interconnect between the polysilicon gate 110 and composite 180 involves quite a number of steps and is space consuming due to the need to build the vertical contacts 182, 184 and the array of metal traces of the metal 1 layer 170. The present invention seeks to provide a simpler, more cost effective, and more compact solution for interconnecting regions in a semiconductor device, without requiring extra process steps.